1/8 AN1301 application note november 2003 1.0 general description the ste100p, also referred to as stephy1, is a high performance fast ethernet physical layer interface for 10base-t and 100base-tx applications. it was designed with advanced cmos technology to provide a media independent interface (mii) for easy attachment to 10/100 media access controllers (mac) and a physical me- dia interface for 100base-tx and 10base-t. the twisted pair interface directly drives a 10/100 twisted pair connection. ste100p is an excellent device perfectly suited for hub, switch, router and other embedded ether- net applications. the system diagram is as shown below: figure 1. system diagram of the ste100p application 2.0 features n integrates the whole physical layer functions of the 100base-tx and 10base-t n 3.3v low power operation n the hardware control pins set the initial state of the ste100p at power-up n designed with a power down feature, which can save the power consumption significantly n can operate for either full duplex or half duplex network applications. n mii interface n provides auto-negotiation, parallel detection or manual control for mode setting n provides mlt-3 transceiver with dc restoration for base-line wander compensation boot rom 25 mhz crystal rj-45 ste100p stephy1 serial eeprom leds pci interface m ac device transformer ste100p - single port fast ethernet transceiver
2/8 AN1301 application note n provides transmit wave-shaper, receive filters, and adaptive equalizer n provides loop-back modes for diagnostic testing n builds in stream cipher scrambler/descrambler and 4b/5b encoder/decoder n supports external transmit transformer with turn ratio 1:1 n supports external receive transformer with turn ratio 1:1 3.0 design and layout guidelines 3.1 general guidelines n verify that all components meet application requirements. n design in filters for the analog power circuits. n use bulk capacitors (10-22uf) between the power and ground planes to minimize switching noise, par- ticularly near high-speed busses (>25 mhz). n use an ample supply of 0.1uf decoupling capacitors to reduce high-frequency noise on the power and ground planes. n use a single analog power and ground plane for multiple devices. keep ferrite bead currents under 65% of the rated load n avoid breaks in the ground plane, especially in areas where it is shielding high-frequency signals. n keep power and ground noise levels below 50mv n keep high-speed signals out of the area between ste100p and the magnetics n ensure that the power supply is rated for the load and that output ripple is minimal (<50mv) n route high-speed signals next to a continuous, unbroken ground plane. n provide impedance matching on long traces to prevent reflections. n do not route any digital signals between the ste100p and the rj-45 connectors at the edge of the board n it is recommended to fill in unused areas of the signal planes with solid copper and attach them with vias to a vcc or ground plane that is not located adjacent to the signal layer. 3.2 differential signal layout guidelines n route differential pairs close together and away from everything else n keep both traces of each differential pair as close to the same length as possible. n avoid vias and layer changes n keep transmit and receive pairs away from each other. run orthogonally, or separate with a ground plane layer. 3.3 power and ground in order to obtain high speed communications design, the power and ground planes may be conceptually divid- ed into three regions (the analog and digital power planes and the signal ground plane) the analog power region extends from the magnetics back to the ste100p, whereas the digital power region extends from the mii interfaces of the ste100p through the rest of the board. only components and signals pertaining to the particular interface should be placed or routed through each respective region. the digital sec- tion supplies power to the digital vcce/i pin and to the external components. the analog section supplies power to vcca pins of the ste100p. the signal ground region is one continuous, unbroken plane that extends from the magnetics through the rest
AN1301 application note 3/8 of the board. the signal ground plane may be combined with chassis ground or isolated from it. if the ground planes are combined, an isolation area is not required. when laying out ground planes, special care must be taken to avoid creating loop antenna effect. some guidelines are as follows- n run all ground plane as solid square or rectangular regions n avoid creating loops with ground planes around other planes 3.4 recommendations the following recommendations apply to design and layout of the power and ground planes and w ill prevent the most common signal and noise issues. n divide the vcc plane into two sections - analog and digital. the break between the planes should run under the device. n when dividing the vcc plane, it is not necessary to add extra layers to the board. simply crate moats or cutout regions in existing layers. n place a high-frequency bypass cap (0.1uf) near each analog vcc pin n join the digital and analog sections at one or more points by ferric beads. ensure that the maximum current rating of the bead is at least 150% of the nominal current that is expected to flow through it. (250ma per ste100p) n place a bulk capacitor (22uf) on each side of each ferrite bead to stop switching noise from travelling through the ferrite. for designs with multiple ste100ps, it is acceptable to supply all from one analog vcc plane. this plane can be joined to the digital vcc plane at multiple points, with a ferrite bead at each one. 4.0 twisted pair interface 4.1 transmit interface circuitry figure 2 shows a typical transmit interface circuitry. current is sourced by the avddt output to the centertap of the primary side of the winding. current flows from the centertap to tx+ and tx-. other components are as fol- lows: n r1 and r2 are 49.9 ohm resistors that provide impedance matching to the line, which has a nominal impedance of 100 ohm. n c1 shunts any common-mode energy present in the output to ground. n the magnetics consists of the main winding and a common-mode choke. n the common-mode choke stops common mode energy from reaching the line. it works together with capacitor c1 to direct common-mode energy away from the line.
4/8 AN1301 application note figure 2. transmit interface circuitry 4.2 receive termination circuitry the receive termination circuit as shown in figure 3 is a simple 100 ohm, 1% resistor across the rx+/ rx- pair. the receive circuit consists of magnetics, which include a main winding and a common-mode choke, and termination resistance to match the line impedance. the common-mode choke can be located on either the primary or secondary side of the winding. some vendors place the receive com- mon-mode choke on the line-side (primary) of the main winding while others place it on the device side (secondary). either location is acceptable. figure 3. receive interface circuitry
AN1301 application note 5/8 4.3 standard termination st recommends a standard termination for the unused pairs on the twisted-pair interface as shown in figure 4. the termination basically looks like a 100 ohm load, matched to the line, which is by passed to chassis ground. this termination is added for robustness and noise reduction. figure 4. suggested termination circuit 5.0 crystal requirements the crystal to be used with the ste101p should be a 25 mhz fundamental mode crystal operating in par- allel resonance, connected as shown in the sample application circuit schematic (see section 7.1). the following table shows the specifications for the crystal: table 1 parameter units min max nom frequency mhz - - 25.0 frequency stability ppm - + 50 - load capacitance pf 18 shunt capacitance pf 8
6/8 AN1301 application note 6.0 led pins the led display, consists of five leds having the following characteristics: n speed led: 100mbps(on) or 10mbps(off) n transmit/receive led: blinks at 10hz when transmitting or receiving, but not colliding n 10mbps led: blinks at 10hz when transmitting, but not colliding n link led: on when 100m or 10m link ok n collision/fd led: blinks at 20hz to indicate a collision. on to indicate full duplex operation 7.0 typical application while the ste100p may be used in a variety of applications such as multi-port repeaters or switches, the application shown below gives a very simple way of evaluating and using the ste100p with minimum cir- cuitry. (refer to bill of materials in table 2) a typical application of the ste100p presented here would be in designing a fast ethernet transceiver with a standard mii interface and a 10/100 mbps twisted pair connector. (refer to fig. 5) in this application, n ste100p is the only ic needed. n it connects directly to the industry standard 40-pin mii connector. n it also connects to the rj-45 jack via a standard fast ethernet transformer. n 5, 4-position dip switches are used to select the phy address. (more details on the phy address reg- isters, etc. are available on the ste100p datasheet) n 2, 10-position dip switches are used for determination of all of the pin-selectable options of the ste100p such as duplex mode, data rate and auto negotiation. n ste100p also supports the mii mdio access to all of its internal registers. n leds are included to indicate status information such as speed, duplex mode, transmit and receive ac- tivity and link status. n there are registers with 16 bits each supported for ste100p. (more details on these registers are avail- able in the ste100p datasheet). n there are also 4 special registers for advanced chip control and status information. 7.1 schematics the schematics for the sample application can be found on the the following page and the st website at: http://www.st.com/prodpres/dedicate/telecom/network/datacom/st100p.htm
AN1301 application note 7/8 a a b b c c d d e e 4 3 2 1 don't stuff l3 if both u4 & u6 are used. notes: - x 1 is suggested to be 25mhz +/-50ppm, with c l = 18pf, and 8pf max shunt capacitance stfephy1 <00> fast ethernet single phy evaluation board b 11 thursday, october 26, 2000 stmicroelectronics, inc. 1310 electronics drive mail station 764 carrollton, tx 75006-5039 title size document number rev date: sheet of chassis avddt rx- rx+ tx- tx+ rxd0 txd0 txd0 txd3 crs tx_en txd2 rxd2 mdc mdc rxd 1 tx_en txd1 rx_clk rx_dv tx_er rx_clk tx_clk rxd0 rxd3 tx_er rx_er rx_er col crs rxd1 rxd 2 mdio col tx_clk txd2 txd3 rx_dv txd1 mdio rxd3 avddt mdint leds ledc ledtr cfg1 cfg0 reset rip pwrdwn mdio mdc rxd 3 rxd2 rxd 1 rxd0 rx_dv rx_clk rx_er tx_er tx_clk tx_en txd 0 txd1 txd 2 txd3 crs col x1 x2 mf4 fde mf2 mf1 mf3 mf0 cfg0 cfg1 pwrdwn fde reset mf0 mf1 mf2 mf3 mf4 led10 ledtr ledl ledl ledc leds gnd led10 v3.3 v3.3 gnd v3.3t vdd vdd vdd agnd gnd agnd agnd gnd agnd agnd gnd gnd gnd vcca gnd agnd gnd gnd agnd vcca gnd vdd v3.3t v3.3 r31 10k r39 1.1k r34 240 r25 10k r15 0 u5 miitest 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 +5v mdio mdc rxd<3> rxd<2> rxd<1> rxd<0> rx_dv rx_clk rx_er tx_er tx_clk tx_en txd<0> txd<1> txd<2> txd<3> col crs gnd r33 240 r26 10k c3 22uf c57 0.1uf d2 led r36 240 c58 0.1uf r38 1.1k r13 10k d5 led r27 10k c59 0.1uf r41 1.1k r350 91 c56 0.1uf r28 10k r20 10k r371 340 tp11 1 c61 0.1uf r14 10k r330 91 r340 91 c55 0.1uf c2 0.1uf r362 0 c54 0.1uf r360 91 r29 10k r10 10k r21 10k r363 0 u1 mii 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 +5v mdio mdc rxd<3> rxd<2> rxd<1> rxd<0> rx_dv rx_clk rx_er tx_er tx_clk tx_en txd<0> txd<1> txd<2> txd<3> col crs +5v +5v gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd +5v l2 bead r364 0 r11 10k r16 10k r361 0 c53 22uf r5 49.9 r365 0 c52 22uf j1 rj45 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 r17 10k r366 0 c4 22uf u6 3.3vreg-l4931cz33 in gnd out r22 10k r4 49.9 r320 91 r9 49.9 c6 10pf r8 75 r35 240 tp12 1 u3 hb626-1 1 2 3 6 7 8 9 10 11 14 15 16 td+ ct td- rd+ ct rd- rx- ct rx+ tx- ct tx+ r23 10k c7 0.1uf d4 led tp13 1 c10 0.1uf r3 0 sw8 1 2 3 4 5 6 7 8 9 15 14 13 12 11 10 18 19 20 17 16 r40 1.1k tp15 1 sw9 1 2 3 4 5 6 7 8 9 15 14 13 12 11 10 18 19 20 17 16 c11 0.1uf r18 0 ohm r1 49.9 tp14 1 l3 bead r32 240 c9 0.001uf r2 49.9 tp8 1 d1 led r7 75 r19 10k c5 10pf tp1 1 d3 led r37 1.1k r6 100 x1 25mhz c8 0.1uf r30 10k r24 10k c1 0.1uf c13 22pf c51 22uf l1 bead c50 22uf c12 22pf sw7 sw dip-4 1 2 3 4 8 7 6 5 r369 340 r12 4.99k sw6 sw dip-4 1 2 3 4 8 7 6 5 u4 3.3vreg-l4931cz33 in gnd out r367 340 u2 stfephy 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 mf4 mf3 mf2 mf1 mf0 fde gnde/i gnda vcca gnda x2 x1 vcca gnda iref vcca vcca rxn rxp gnda txp vcca txn gnda gnde test pwrdwn reset rip nc nc nc scan_en leds ledc ledl ledtr ledr10 vcce gnde mdio mdc rxd3 rxd2 vcce/i rxd1 rxd0 rx_dv rx_clk gnde/i rx_er/rxd4 tx_er/txd4 tx_clk tx_en txd0 txd1 txd2 txd3 col crs fds/mdint vcce/i cfg1 cfg0 r370 340 sw3 sw dip-4 1 2 3 4 8 7 6 5 sw5 sw dip-4 1 2 3 4 8 7 6 5 r368 340 sw4 sw dip-4 1 2 3 4 8 7 6 5
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com 8/8 AN1301 application note 7.2 bill of materials following are the bill of materials for the ste100p sample application. item qty reference part __________________________________________________________________ 1 13 c1,c2,c7,c8,c10,c11,c54, 0.1uf c55,c56,c57,c58,c59,c61 2 6 c3,c4,c50,c51,c52,c53 22uf 3 2 c5,c6 10pf 4 1 c9 0.001uf 5 2 c12,c13 22pf 6 5 d1,d2,d3,d4,d5 led 7 1 j1 rj45 8 3 l1,l2,l3 bead (do not install l3 if u4 & u6 both installed) 9 5 r1,r2,r4,r5,r9 49.9 10 8 r3,r15,r361,r362,r363, 0 ohm r364,r365,r366 11 1 r6 100 ohms 12 2 r8,r7 75 ohms 13 19 r10,r11,r13,r14,r16,r17, 10k r19,r20,r21,r22,r23,r24, r25,r26,r27,r28,r29,r30, r31 14 1 r12 4.99k 15 1 r18 0 ohm 16 5 r32,r33,r34,r35,r36 240 ohms 17 5 r37,r38,r39,r40,r41 1.1k 18 5 r320,r330,r340,r350,r360 91 ohms 19 5 r367,r368,r369,r370,r371 340 ohms 20 5 sw3,sw4,sw5,sw6,sw7 dip switch dip-4 21 2 sw8,sw9 sw dip-10 22 7 tp1,tp8,tp11,tp12,tp13, test pins tp14,tp15 23 1 u1 mii 40 pin connector 24 1 u2 stephy ste100p 25 1 u3 hb626-1 transformer 26 2 u4,u6 3.3vreg-l4931cz33 27 1 u5 miitest header 28 1 x1 25mhz crystal
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